1. Technical Field
The invention relates to semiconductor memory devices and, more particularly, to a resetable redundancy circuit for a semiconductor memory device.
2. Discussion of Related Art
The demand for large highly integrated memory devices continues to increase with the increasing consumer demand for portable electronic devices (such as computers, digital cameras, music players etc.) and appliances increases. As the capacity (e.g., gigabytes) of semiconductor memory devices increases, there is a greater likelihood that a few defective memory cells will be created due to defects and contaminants in the fabrication of the memory devices. If the memory device includes at least one defective cell, it will not work and be treated as a defective product unless it can be “repaired”.
To discard defective memory devices reduces the yield especially in the case there is a higher likelihood of creating a few defective cells due to the increasing integration (capacity) of the semiconductor memory devices. Redundant memory cells are provided to increase the yield of memory devices. A redundant cell, row, or column of cells can be used to salvage devices having fewer than a specified number of defective cells, and thus increase yield. As memories become larger, the yield of perfect memory chips becomes lower, since having a larger number of cells on a silicon chip provides more opportunity for defective cells.
A redundancy circuit fabricated with the memory device is provided to reduce the loss of memory chips due to defects of the memory devices caused by the above-stated defects and contaminants. The redundancy circuit includes an array of “spare” memory cells (a redundancy cell array) that can be used in a substituted manner instead of the anticipated few defective memory cells. Redundancy memory elements are formed by memory cells identical to the memory cells of the memory matrix, and are arranged in rows (redundancy rows) or columns (redundancy columns). The redundancy circuit controls the selection of a given redundancy row or redundancy column in substitution for a defective row or column of the main memory matrix, i.e., a row or column in which at least one defective memory cell is detected.
Repair methods using such a redundancy circuit include: a physical method of burning and cutting a fuse or making a junction to be short-circuited with for example a laser beam; a method of electrically melting and cutting a fuse by flowing over-current through it; an electric fuse method of programming with EPROM memory cells, and the like.
Hereinafter, a conventional redundancy circuit will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of a redundancy circuit used in a conventional physical repair method using a laser beam.
Referring to FIG. 1, the redundancy circuit is composed of a redundancy enable fuse F1 for enabling the redundancy circuit; several fuse boxes 2 for receiving addresses A0P, A1P, . . . , AiP, . . . , AnP to program an address that specifies one defective cell; one or more NAND-gates NAND1, . . . , NANDm for receiving comparison signals RA0P, RA1P, . . . , RAiP, . . . , RAnP output by the fuse boxes 2 and generating a NAND output; a NOR-gate NOR1 for receiving output signals from the NAND-gates NAND1, . . . , NANDm and generating a NOR output; a first master signal FUSE_EN and a second (complementary) master signal FUSE_ENB for controlling the overall redundancy circuit including the redundancy enable fuse F1 and the fuse boxes 2; a first inverter INV1 for generating the first master signal FUSE_EN; a second inverter INV2 for generating the second master signal FUSE_ENB; and NMOS transistors N1, . . . , Nm that receive the second master signal FUSE_ENB as a gate input and are connected between the NAND-gates NAND1, . . . , NANDm and a ground terminal. Here, the NOR-gate NOR1 generates an enable signal RD_i for enabling a redundancy decoder (not shown).
FIG. 2 is a detailed circuit diagram of a fuse box in the redundancy circuit of FIG. 1.
Referring to FIG. 2, the fuse box is composed of a third inverter INV3, a pair of CMOS transistors 4 and 14, and address fuses 6 and 16. If the address AiP is high, the third inverter INV3 converts the address AiP from high to low. The high signal is inputted to the CMOS transistor 14 and the low signal is inputted to the CMOS transistor 4. The other ends of the CMOS transistors 4 and 14 are connected to the address fuses 6 and 16, respectively. The state of the comparison signal RAiP, which is an output of the fuse box, is determined depending on the input address by physically cutting one of the address fuses 6 and 16 with the laser beam.
Referring to FIGS. 1 and 2, the comparison signals RAiP are required to be high to enable the redundancy circuit. That is, the comparison signals RA0P, RA1P, RAiP, . . . , RAnP are subject to NAND operation in the NAND-gates NAND1, . . . , NANDm. The NAND-gates NAND1, . . . , NANDm will all output a low output when the comparison signals RA0P, RA1P, RAiP, . . . , RAnP input to the NAND-gates NAND1, . . . , NANDm are all high. As a result, the NOR-gate NOR1, which receives all low signals, outputs the high enable (match) signal RD_i.
To repair a defective cell using the redundancy circuit, the redundancy enable fuse F1 is first cut by the laser beam. In this case, the first master signal FUSE_EN becomes high and the second master signal FUSE_ENB becomes low. Accordingly, the CMOS transistors 4 and 14 in the fuse box 2 are all turned on and the NMOS transistors N1, . . . , Nm are all turned off, enabling the redundancy circuit. The repair is completed by cutting one of the two address fuses 6 and 16 in the fuse box 2 corresponding to an opposite state of an address indicating a defective cell. When the repair is completed and then the same address as the stored address is input to the redundancy circuit while the semiconductor memory device operates, the comparison signals RA0P, RA1P, RAiP, . . . , RAnP become all high and the enable signal RD_i becomes high through the NAND-gates N1, . . . , Nm and the NOR-gate. The enable (match) signal RD_i is used to disable a main decoder (not shown) and enable the redundancy decoder, such that the redundancy cell is substituted for the defective cell.
However, there is a limitation with the above-described physical repair method in which a fuse is cut using a laser beam in that additional repairing is not allowed to be performed when a defective cell is created following a repairing or packaging process.
There is another problem with the physical repair method in which a fuse is cut using the laser beam in that the use of the method adds a separate additional process in fabricating a semiconductor memory device.